
CY28445-5
..................... Document #: 38-07739 Rev *C Page 23 of 25
Note:
1. Measured under typical condition.
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the test load configuration of single-ended PCI, USB output signals.
TPERIODAbs
Absolute Period
Measurement at 1.5V
20.48125
21.18542
ns
THIGH
48_M High time
Measurement at 2.4V
8.094
11.036
ns
TLOW
48_M Low time
Measurement at 0.4V
7.694
10.836
ns
TR / TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
2.2
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
350
ps
LACC
48M Long Term Accuracy
Measured at crossing point VOX
–
100
ppm
27_M at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Spread Disabled 27M Period
Measurement at 1.5V
27.000
27.0547
ns
Spread Enabled 27M Period
Measurement at 1.5V
27.000
27.0547
THIGH
27_M High time
Measurement at 2.0V
10.5
–
ns
TLOW
27_M Low time
Measurement at 0.8V
10.5
–
ns
TR / TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
500
ps
LACC
27_M Long Term Accuracy
Measured at crossing point VOX
–0
ppm
REF at 3.3V
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
REF Period
Measurement at 1.5V
69.8203
69.8622
ns
TPERIODAbs
REF Absolute Period
Measurement at 1.5V
68.82033
70.86224
ns
TR / TF
REF Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
0.9
4.0
V/ns
TSKEW
REF Clock to REF Clock
Measurement at 1.5V
–
500
ps
TCCJ
REF Cycle to Cycle Jitter
Measurement at 1.5V
–
1000
ps
LACC
Long Term Accuracy
Measurement at 1.5V
–
300
ppm
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
–
1.8
ms
TSS
Stopclock Set-up Time
10.0
–
ns
TSH
Stopclock Hold Time
0
–
ns
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
Figure 14. Single-ended PCI, USB Load Configuration
5 pF